Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Code compression for low power embedded system design
Proceedings of the 37th Annual Design Automation Conference
Design and simulation of a pipelined decompression architecture for embedded systems
Proceedings of the 14th international symposium on Systems synthesis
Multi-profile based code compression
Proceedings of the 41st annual Design Automation Conference
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Study on LZW algorithm for embedded instruction memory
IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
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Code compression, initially conceived as an effective technique to reduce code size in embedded systems, today also brings advantages in terms of performance and energy consumption, due to an increase in the cache hit ratio. This paper proposes the design of a code decompressor engine for our dictionary-based method, embedding it into the Leon (SPARC V8) processor. Our design guarantees that the processor cycle-time is maintained and the decompression is performed on-the-fly. We have achieved a functional implementation on a FPGA, with compression ratios ranging from 72% to 88%, performance improvement as high as 45% and a reduction on energy consumption reaching 35%, validated through two real-world benchmarks suites: MediaBench and MiBench. We also explore some trade-offs between compression ratio and performance.