Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Selective instruction compression for memory energy reduction in embedded systems
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Profile-guided code compression
PLDI '02 Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation
Design of an one-cycle decompression hardware for performance increase in embedded systems
Proceedings of the 39th annual Design Automation Conference
A code decompression architecture for VLIW processors
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Code compression for VLIW processors using variable-to-fixed coding
Proceedings of the 15th international symposium on System Synthesis
A decompression core for powerPC
IBM Journal of Research and Development
Compact Binaries with Code Compression in a Software Dynamic Translator
Proceedings of the conference on Design, automation and test in Europe - Volume 2
LZW-Based Code Compression for VLIW Embedded Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Compiler-Guided data compression for reducing memory consumption of embedded applications
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Profile-driven compression scheme for embedded systems
Proceedings of the 3rd conference on Computing frontiers
A software-only compression system for trading-offs between performance and code size
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Code compression for performance enhancement of variable-length embedded processors
ACM Transactions on Embedded Computing Systems (TECS)
Code compression for VLIW embedded systems using a self-generating table
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Access pattern-based code compression for memory-constrained systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Selective Code Compression Scheme for Embedded Systems
Transactions on High-Performance Embedded Architectures and Compilers I
A universal placement technique of compressed instructions for efficient parallel decompression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimizing area costs in GPS applications on a programmable DSP by code compression
SOC'09 Proceedings of the 11th international conference on System-on-chip
Profile-driven selective program loading
EuroPar'10 Proceedings of the 16th international Euro-Par conference on Parallel processing: Part I
Code compression for embedded VLIW processors using variable-to-fixed coding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Code compression and decompression for coarse-grain reconfigurable architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cost Minimization with HPDFG and Data Mining for Heterogeneous DSP
Journal of Signal Processing Systems
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In the embedded system design, memory is one of the most restricted resources. Code compression has been proposed as a solution to reduce the code size of applications for embedded systems. Data compression techniques are used to compress programs to reduce memory size. Most previous work compresses all instructions found in an executable, without taking into account the program execution profile. In this paper, a profile-driven code compression design methodology is proposed. Program profiling information can be used to help code compression to selectively compress non-critical instructions, such that the system performance degradation due to the decompression penalty is reduced.