Space- and Time-Efficient Decoding with Canonical Huffman Trees
CPM '97 Proceedings of the 8th Annual Symposium on Combinatorial Pattern Matching
Code Compression Using Variable-to-fixed Coding Based on Arithmetic Coding
DCC '03 Proceedings of the Conference on Data Compression
LZW-Based Code Compression for VLIW Embedded Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 3
A decompression core for powerPC
IBM Journal of Research and Development
A hamming distance based VLIW/EPIC code compression technique
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
A post-compilation register reassignment technique for improving hamming distance code compression
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Data Compression: The Complete Reference
Data Compression: The Complete Reference
Efficient code density through look-up table compression
Proceedings of the conference on Design, automation and test in Europe
Code compression for embedded VLIW processors using variable-to-fixed coding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 46th Annual Design Automation Conference
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VLIW processors provide higher performance and better efficiency etc. than RISC processors in specific domains like multimedia applications etc. A disadvantage is the bloated code size of the compiled application code. Therefore, reducing the application code size is a design key issue for VLIW processors. In this paper we adapt a hardware-supported approach called "Deflate" [12] which has been used before in data compression. It can significantly reduce the code size compared to state-of-the-art approaches for VLIW processors as we will show within this work. In fact, we enhance the "Deflate" algorithm by using a new technique called Filled Buffer Technique which can be applied to any Lempel-Ziv family algorithms to improve compression ratio in average by more than 13% compared to the sole "Deflate" algorithm. Using our Filled Buffer Technique in conjunction with "V2F" [15] improves the compression ratio by 10%. We have conducted evaluations using a representative set of benchmarks (from Mediabench and Mibench) and have applied our scheme to two VLIW processors, namely TMS320C62x and TMS320C64x. We achieved allover compression ratios as low as 44% using the "Deflate" algorithm (61% and 56% in average for TMS320C62x and TMS320C64x, respectively).