Adaptive object code compression
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Code compression for VLIW embedded systems using a self-generating table
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FBT: filled buffer technique to reduce code size for VLIW processors
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A universal placement technique of compressed instructions for efficient parallel decompression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Embedded computing systems are space and cost sensitive; memory is one of the mostrestricted resources, posing serious constraints on program size. Code compression,which is a special case of data compression where the input source is machineinstructions, has been proposed as a solution to this problem. Previous work in codecompression has focused on either fixed-to-variable coding or dictionary-basedalgorithms. We propose code compression schemes that use variable-to-fixed (V2F)length coding, based on arithmetic coding. Experiments show that the compression ratiousing memoryless V2F coding for the TMS320C6x processor is on average 82.5%(defined as the ratio of the compressed over the uncompressed program) anddecompression can be parallelized. A Markov-based V2F coding based on arithmeticcoding, can achieve an average compression ratio 72% for TMS320C6x, whiledecompression cannot be parallelized. Furthermore, our experiments have shown thatarithmetic coding based V2F coding has similar compression performance with Tunstallcoding. Finally, we present a power reduction scheme for the instruction bus using ourV2F coding scheme.