Post-compilation optimization for multiple gains with pattern matching

  • Authors:

  • Rajeev Kumar;Amit Gupta;B. S. Pankaj;Mrinmoy Ghosh;P. P. Chakrabarti

  • Affiliations:

  • Indian Institute of Technology Kharagpur, Kharagpur, WB, India;Indian Institute of Technology Kharagpur, Kharagpur, WB, India;Indian Institute of Technology Kharagpur, Kharagpur, WB, India;Indian Institute of Technology Kharagpur, Kharagpur, WB, India;Indian Institute of Technology Kharagpur, Kharagpur, WB, India

  • Venue:
  • ACM SIGPLAN Notices
  • Year:
  • 2005

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Abstract

Many existing retargetable compilers for ASIPs and domain-specific processors generate low quality code since the compiler is not able to fully utilize the intricacies of ISA of these processors. Hence, there is a need to further optimize the code produced by these compilers. In this paper, we introduce a new post-compilation optimization technique which is based on finding repeating instruction patterns in generated code and replacing them with their optimized equivalents. The instruction patterns to be found are represented by finite state machines which allow encapsulation of multiple patterns in just one representation, and instructions in a pattern to be not necessarily lexically adjacent. We also present a conflict resolution algorithm to select an optimization whenever a set of instructions fall under two or more different patterns of which only one can be applied on the basis of code size, cycle count or switching activity improvement. We tested this technique on the compiled binaries of ARM and Intel processors for code size improvement. We discuss the possible applications of this strategy in design space exploration (DSE) of embedded processors.