A VLIW-based post compilation framework for multimedia embedded DSPs with hardware specific optimizations

Authors:
Meng-Hsuan Cheng;Kenn Slagter;Tai-Wen Lung;Yeh-Ching Chung
Affiliations:
System Software Laboratory, Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.C.;System Software Laboratory, Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.C.;System Software Laboratory, Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.C.;System Software Laboratory, Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.C.
Venue:
MTPP'10 Proceedings of the Second Russia-Taiwan conference on Methods and tools of parallel programming multicomputers
Year:
2010

Citing 15
Cited 0

Advanced compiler optimizations for supercomputers

Communications of the ACM - Special issue on parallelism
IMPACT: an architectural framework for multiple-instruction-issue processors

ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Engineering a simple, efficient code-generator generator

ACM Letters on Programming Languages and Systems (LOPLAS)
Compiler transformations for high-performance computing

ACM Computing Surveys (CSUR)
Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints

CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
Post-pass binary adaptation for software-based speculative precomputation

PLDI '02 Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation
Code Generation for Embedded Processors

Code Generation for Embedded Processors
Binary translation to improve energy efficiency through post-pass register re-allocation

Proceedings of the 4th ACM international conference on Embedded software
A post-compiler approach to scratchpad mapping of code

Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
SIMD Optimization in COINS Compiler Infrastructure

IWIA '05 Proceedings of the Innovative Architecture on Future Generation High-Performance Processors and Systems
Post-compilation optimization for multiple gains with pattern matching

ACM SIGPLAN Notices
Compilers: Principles, Techniques, and Tools (2nd Edition)

Compilers: Principles, Techniques, and Tools (2nd Edition)
Computer Architecture, Fourth Edition: A Quantitative Approach

Computer Architecture, Fourth Edition: A Quantitative Approach
Scalable Vector Processors for Embedded Systems

IEEE Micro
A retargetable VLIW compiler framework for DSPs with instruction-level parallelism

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

In high performance and low power multimedia embedded system design, VLIW-based embedded DSPs compilers that exploit ILP have become popular and play an important role today. For this reason, we need optimizing embedded DSP compilers that can both generate capable and efficient code in terms of performance, power, size, and productivity. In this paper, we show a post-compilation framework that can further optimize programs that have already been compiled and optimized by another compiler, by using runtime information and exploiting hardware specific features of DSPs. Finally, we show in our simulation results, that even programs compiled at the best optimization level, can obtain significant improvement through the use of this framework.