Instruction-level parallel processing: history, overview, and perspective
The Journal of Supercomputing - Special issue on instruction-level parallelism
Improvements to graph coloring register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Instruction fetch mechanisms for VLIW architectures with compressed encodings
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Modulo scheduling for the TMS320C6x VLIW DSP architecture
Proceedings of the ACM SIGPLAN 1999 workshop on Languages, compilers, and tools for embedded systems
Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Compiler optimization and ordering effects on VLIW code compression
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
LZW-Based Code Compression for VLIW Embedded Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 3
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This paper describes the development and compiler utilization of variable length instruction set extensions to an existing high-performance, 32-bit VLIW DSP processor. We describe how the instruction set extensions (1) reduce code size significantly, (2) are binary compatibile with older object code, (3) do not require the processor to switch "modes", and (4) are exploited by a compiler. We describe the compiler strategies that utilize the new instruction set extensions to reduced code size. When compiling our benchmark suite for best performance, we show that our compiler uses the variable length instructions to decreases code size by 11.5 percent, with no reduction in performance. We also show that our implementation allows a wider code size and performance tradeoff range than earlier versions of the architecture.