A low latency wormhole router for asynchronous on-chip networks
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and significan parametric variations. Asynchronous circuits have the great potential to achieve delay insensitive, high performance and low power nanoelectronic design, while the existing asynchronous circuits do not guarantee logic and timing correctness in the presence of glitches. In this paper, I propose robust differential asynchronous (RDA) circuits, which combine asynchronous circuits for delay insensitiveness, differential logic for redundancy, and error detection codes for resilience. Theoretical analysis and SPICE simulation based on 22nm CMOS Predictive Technology Models show that the proposed RDA circuits achieve much enhanced reliability in (1) logic correctness at the event of a single bit soft error or common multiple bit soft errors by differential logic and error detection codes, and (2) timing correctness for any delay variation given physical proximity of the circuit components, with comparable area overhead to existing asynchronous circuits.