The Partial Reverse If-Conversion Framework for Balancing Control Flow and Predication
International Journal of Parallel Programming
Scalable Parallel Programming with CUDA
Queue - GPU Computing
A view of the parallel computing landscape
Communications of the ACM - A View of Parallel Computing
Heterogeneous vs homogeneous MPSoC approaches for a mobile LTE modem
Proceedings of the Conference on Design, Automation and Test in Europe
MARC: A Many-Core Approach to Reconfigurable Computing
RECONFIG '10 Proceedings of the 2010 International Conference on Reconfigurable Computing and FPGAs
Reducing branch divergence in GPU programs
Proceedings of the Fourth Workshop on General Purpose Processing on Graphics Processing Units
OpenCL and the 13 dwarfs: a work in progress
ICPE '12 Proceedings of the 3rd ACM/SPEC International Conference on Performance Engineering
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Open Compute Language (OpenCL) has been proposed as a platform-independent parallel execution framework to target multicores, graphics processing units (GPUs), digital signal processors (DSPs), and other custom accelerators. Traditionally OpenCL is designed to scale across system generations by having each new model increase the available resources: processing cores, register file entries, and shared (localized) physical memory. However, when evaluating all potential models capable of running OpenCL the numerous performance trade-offs associated with these competing resources makes for a large exploration space. Specifically there are advantages to systematically analyzing the OpenCL parallel expressions to eliminate processor elements that constrain the overall design. We have designed an analysis tool for evaluating OpenCL kernels and the potential processor configurations in FPGA-based multiprocessor systems-on-chip (MPSoC) designs. The Flexible OpenCL (FlexCL) system determines integrated hardware-software customization opportunities related to processor design across sets of OpenCL applications. The paper provides an evaluation of various OpenCL components synthesized to FPGA-based multicore design alternatives.