Reconfigurable Architecture for Deinterlacer based on Algorithm/Architecture Co-Design

Authors:
Gwo Giun Lee;Ming-Jiun Wang;Bo-Han Chen;Jiunfu Chen;Ping-Keng Jao;Ching Jui Hsiao;Ling-Fei Wei
Affiliations:
Media SoC Lab., Department of Electrical Engineering, National Cheng Kung University, Taiwan, R.O.C. 701;Media SoC Lab., Department of Electrical Engineering, National Cheng Kung University, Taiwan, R.O.C. 701;Media SoC Lab., Department of Electrical Engineering, National Cheng Kung University, Taiwan, R.O.C. 701;Media SoC Lab., Department of Electrical Engineering, National Cheng Kung University, Taiwan, R.O.C. 701;Media SoC Lab., Department of Electrical Engineering, National Cheng Kung University, Taiwan, R.O.C. 701;Media SoC Lab., Department of Electrical Engineering, National Cheng Kung University, Taiwan, R.O.C. 701;Media SoC Lab., Department of Electrical Engineering, National Cheng Kung University, Taiwan, R.O.C. 701
Venue:
Journal of Signal Processing Systems
Year:
2011

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Abstract

This paper presents the algorithm and reconfigurable architecture of motion-adaptive deinterlacer for high-definition video. The content-adaptability of algorithm and the reconfiguration of architecture are concurrently explored by algorithm/architecture co-design methodology and Caltrop actor language (CAL) modeling of the dataflow. In the design methodology we employed, the CAL dataflow model is also very helpful in the verification of our deinerlacer. The proposed algorithm and architecture design of deinterlacer is more cost-efficient than two recently proposed works in terms of algorithmic performance and silicon area of VLSI implementation. Moreover, data path reconfiguration efficiently enables various interpolation schemes using less computational resource of hardware than non-reconfigurable architecture.