A Theory for Multiresolution Signal Decomposition: The Wavelet Representation
IEEE Transactions on Pattern Analysis and Machine Intelligence
Introduction to compiler construction
Introduction to compiler construction
Methodical Low-Power ASIP Design Space Exploration
Journal of VLSI Signal Processing Systems
Architecture Exploration for Embedded Processors with Lisa
Architecture Exploration for Embedded Processors with Lisa
Circuit Design with VHDL
Custom Instruction Filter Cache Synthesis for Low-Power Embedded Systems
RSP '05 Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping
An integrated open framework for heterogeneous MPSoC design space exploration
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Embedded Core Design with FPGAs
Embedded Core Design with FPGAs
Customizable Embedded Processors: Design Technologies and Applications
Customizable Embedded Processors: Design Technologies and Applications
Computer Architecture: From Microprocessors to Supercomputers (Oxford Series in Electrical and Computer Engineering)
Power-efficient Instruction Encoding Optimization for Embedded Processors
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Processor Description Languages
Processor Description Languages
A reconfigurable ASIP for convolutional and turbo decoding in an SDR environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The increasing complexity of applications with a decreasing time-to-market requirement has created a strong interest in both high-performance and flexible embedded processors with a strong consideration for battery life. Low-power optimizations are therefore often applied toward the development of Application-Specific Instruction-Set Processors (ASIPs). In this paper ASIP accelerators for a typical DSP task are developed and synthesis results from six different cell-based and FPGA architectures are shown. By carefully analyzing algorithms and implementing appropriate accelerators with logic, it is shown that an increase in design performance is achieved while still reducing energy consumption due to the reduced latency of the task. In addition, we show cases when classic synthesis options can outperform new power optimization features in Xilinx ISE 11.1.