Robust Energy-Efficient Adder Topologies
ARITH '07 Proceedings of the 18th IEEE Symposium on Computer Arithmetic
Design and analysis of hybrid NEMS-CMOS circuits for ultra low-power applications
Proceedings of the 44th annual Design Automation Conference
Integrated circuit design with NEM relays
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
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Nanoelectromechanical systems (NEMS) is an emerging nanoscale technology that combines mechanical and electrical effects in devices. A variety of NEMS-based devices have been proposed for integrated chip designs. Amongst them are near-ideal digital switches. The electromechanical principles that are the basis of these switches impart the capability of extremely low power switching characteristics to digital circuits. NEMS switching devices have been mostly used as simple switches to provide digital operation, however, we observe that their unique operation can be used to accomplish logic functions directly. In this paper, we propose a novel technique called 'weighted area logic' to design logic circuits with NEMS-based switches. The technique takes advantage of the unique structural configurations possible with the NEMS devices to convert the digital switch from a simple ON-OFF switch to a logical switch. This transformation not only reduces the delay of complex logic units, but also decreases the power and area of the implementation further. To demonstrate this, we show the new designs of the logic functions of NAND, XOR and a three input function Y = A + B. C, and compose them into a 32-bit adder. Through simulation, we quantify the power, delay and area advantages of using the weighted area logic technique over a standard CMOS-like design technique applied to NEMS.