Design optimizations for microprocessors at low temperature

  • Authors:
  • Arman Vassighi;Ali Keshavarzi;Siva Narendra;Gerhard Schrom;Yibin Ye;Seri Lee;Greg Chrysler;Manoj Sachdev;Vivek De

  • Affiliations:
  • Intel Labs, Hillsboro, OR;Intel Labs, Hillsboro, OR;Intel Labs, Hillsboro, OR;Intel Labs, Hillsboro, OR;Intel Labs, Hillsboro, OR;Intel Labs, Hillsboro, OR;Intel Labs, Chandler, AZ;University of Waterloo, Canada;Intel Labs, Hillsboro, OR

  • Venue:
  • Proceedings of the 41st annual Design Automation Conference
  • Year:
  • 2004

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Abstract

We investigate trade-offs in microprocessor frequency and system power achievable for low temperature operation in scaled high leakage technologies by combining refrigeration with supply voltage selection, body bias, transistor sizing and shorter channel length. Reducing channel length provides better frequency and power improvement than forward body bias. When, the leakage power is more than 30 of chip power, combining refrigeration with enhancing technology by shorter channel length provides the best trade-off for power and frequency.