Error-control coding for computer systems
Error-control coding for computer systems
A 1.3GHz fifth generation SPARC64 microprocessor
Proceedings of the 40th annual Design Automation Conference
A Synthesizing Method for Large Parallel Counters with a Network of Smaller Ones
IEEE Transactions on Computers
IEEE Transactions on Computers
Counting Responders in an Associative Memory
IEEE Transactions on Computers
Hi-index | 0.00 |
There are situations in a computing system where incoming information needs to be compared with a piece of stored data to locate the matching entry, e.g., cache tag array lookup and translation look-aside buffer matching. If the stored data is protected with error-correcting codes (ECC) for reliability reason, the previous solution is to access the stored information, decode and correct if necessary before it is used to compare with the incoming data. The decoding and correcting step increases the total access time, which is often critical. In this paper, we propose a method to improve the compare latency for information encoded with ECC. We use the cache tag array look-up as an example, and results show that 30% gate count reduction and 12% latency reduction are achieved.