Critical path selection for performance optimization
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Using profile information to assist classic code optimizations
Software—Practice & Experience
Optimally profiling and tracing programs
ACM Transactions on Programming Languages and Systems (TOPLAS)
Hardware/software instruction set configurability for system-on-chip processors
Proceedings of the 38th annual Design Automation Conference
Complex library mapping for embedded software using symbolic algebra
Proceedings of the 39th annual Design Automation Conference
Hardware-software cosynthesis for digital systems
Readings in hardware/software co-design
Scheduling for Embedded Real-Time Systems
IEEE Design & Test
Scratchpad memory: design alternative for cache on-chip memory in embedded systems
Proceedings of the tenth international symposium on Hardware/software codesign
Synchronous path analysis in MOS circuit simulator
DAC '82 Proceedings of the 19th Design Automation Conference
Networks on Chip: A New Paradigm for Systems on Chip Design
Proceedings of the conference on Design, automation and test in Europe
Automatic generation of application specific processors
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Debugging HW/SW interface for MPSoC: video encoder system design case study
Proceedings of the 41st annual Design Automation Conference
Overview of the MPSoC design challenge
Proceedings of the 43rd annual Design Automation Conference
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Using traditional software profiling to optimize embedded software in an MPSoC design is not reliable. With multiple processors running concurrently and programs interacting, traditional profiling on individual processors cannot capture useful execution information to assist software optimization. A new method to model parallel executions of interacting programs is needed. In this paper, we consider the software optimization problem for throughput-constrained MPSoC designs. We define the "longest delay path" as a sequence of steps leading to a throughput constraint violation and propose an algorithm to build up the path dynamically during simulation. Using an industrial-strength MPEG-2 decoder design in our case study and custom instructions for software optimization, we show that we can optimize the software efficiently in MPSoC designs using frequently executed statement information from the longest delay path.