Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Introduction to programmable active memories
Systolic array processors
Mapping systolic arrays onto the map-oriented machine (MoM)
Systolic array processors
High level synthesis of ASICs under timing and synchronization constraints
High level synthesis of ASICs under timing and synchronization constraints
Partial orderings of event sets and their application to prototyping concurrent, timed systems
Journal of Systems and Software - Special issue on applying specification, verification, and validation techniques to industrial software systems
Synthesis fo the hardware/software interface in microcontroller-based systems
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Partitioning and Scheduling Parallel Programs for Multiprocessors
Partitioning and Scheduling Parallel Programs for Multiprocessors
IEEE Design & Test
Software optimization for MPSoC: a mpeg-2 decoder case study
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
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As system design grows increasingly complex, the use of predesigned components, such as general-purpose microprocessors, can simplify synthesized hardware. While the problems in designing systems that contain processors and application-specific integrated circuit chips are not new, computer-aided synthesis of such heterogeneous or mixed systems poses unique challenges. Here, we demonstrate the feasibility of synthesizing heterogeneous systems by using timing constraints to delegate tasks between hardware and software so that performance requirements can be met.