Implementation of the data encryption standard algorithm with FPGAs
Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
A New Control Circuit for Asynchronous Micropipelines
IEEE Transactions on Computers
Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
An Investigation into the Security of Self-Timed Circuits
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Reconfigurable Elliptic Curve Cryptosystems on a Chip
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Implementation of the SHA-2 Hash Family Standard Using FPGAs
The Journal of Supercomputing
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Cryptographic algorithms are usually compute-intensive and more efficiently implemented in hardware than in software. By taking advantage of FPGA technology, some work offers high performance and flexible solutions for cryptographic algorithms. But FPGAs still have some drawbacks. To overcome inherent shortages of FPGA, a novel asynchronous reconfigurable cryptographic engine (ARCEN) is introduced. In this architecture, reconfigurable cryptographic array is the kernel. It routes signals asynchronously between adjacent cells through Neighbor-to-Neighbor wires with 4-phase handshaking protocol. Computation circuit for reconfigurable cell is developed with modified DSDCVS logic. Experiment results show that the architecture has a better performance than FPGA.