Multiplierless multiple constant multiplication
ACM Transactions on Algorithms (TALG)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new algorithm for elimination of common subexpressions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Algorithm for Jointly Optimizing Quantization and Multiple Constant Multiplication
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hi-index | 0.00 |
In this work, the trade-offs in FIR filter design are studied. This includes the adder depth for the constant filter coefficients, the number of adders, and the number of delay elements, i.e., the filter order. It is shown that the proposed design algorithm can be used to decrease both the overall arithmetic complexity and the adder depth, possibly with a small penalty in delay elements. This is achieved by selecting coefficients that can be realized at a lower depth, i.e., the lengths of the logic paths are reduced. Hence, this directly translates into decreased power consumption due to reduced glitch propagation and increased throughput due to a shorter critical path.