High speed multiplier based on the algorithm of Chinese abacus

Authors:
Chien-Hung Lin;Shu-Chung Yi;Jin-Jia Chen
Affiliations:
Department of Electrical Engineering, National Changhua University of Education, Changhua, Taiwan;Graduate Institute of Integrated Circuit Design, National Changhua University of Education, Changhua, Taiwan;Department of Electrical Engineering, National Changhua University of Education, Changhua, Taiwan
Venue:
ACACOS'10 Proceedings of the 9th WSEAS international conference on Applied computer and applied computational science
Year:
2010

Citing 4
Cited 0

Multiplexer-Based Array Multipliers

IEEE Transactions on Computers
The Chinese Abacus Method: Can We Use It for Digital Arithmetic?

GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
The new architecture of radix-4 Chinese abacus adder

ISMVL '06 Proceedings of the 36th International Symposium on Multiple-Valued Logic
A 40-ns 17-Bit by 17-Bit Array Multiplier

IEEE Transactions on Computers

Quantified Score

Hi-index	0.00

Visualization

Abstract

A 4×4 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed and power consumption of the 4×4 bits Braun array multiplier, the delays of the 4-bit abacus multiplier are 19.7% and 10.6% less than that of Braun array multiplier with 0.35µm and 0.18µm technologies, respectively. Meanwhile, the power consumption of the 4-bit abacus multiplier is, respectively, less about 8.7% and 18% also.