Efficient Systolic Array Mapping of FIR Filters Used in PAM-QAM Modulators

Authors:
A. Chorevas;D. Reisis
Affiliations:
Electronics Laboratory, Physics Department, University of Athens, Athens 15784, Greece;Electronics Laboratory, Physics Department, University of Athens, Athens 15784, Greece
Venue:
Journal of VLSI Signal Processing Systems
Year:
2003

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Abstract

This paper presents efficient techniques for mapping FIR filter computation circuits for PAM and QAM modulators onto systolic arrays. The exploitation of the inherent symmetry of these problem instances and the use of Look-Up Tables (L.U.T.) in conjunction with the use of systolic architectures, increases the performance while keeping the VLSI area minimal. Exploiting parallelism and pipelining enhances the throughput and results in linear expandability of the FIR filter with respect to the bit accuracy and to the stage count.