Structure of parallel multipliers for a class of fields GF(2m)
Information and Computation
IEEE Transactions on Computers - Special issue on computer arithmetic
Low-Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields
IEEE Transactions on Computers
Low Complexity Bit-Parallel Multipliers for a Class of Finite Fields
IEEE Transactions on Computers
Multiplexer-Based Array Multipliers
IEEE Transactions on Computers
IEEE Transactions on Computers
Cryptography and Secure Communications
Cryptography and Secure Communications
Handbook of Applied Cryptography
Handbook of Applied Cryptography
Subword Parallelism with MAX-2
IEEE Micro
CMOS Digital Integrated Circuits Analysis & Design
CMOS Digital Integrated Circuits Analysis & Design
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This investigation presents an effective algorithm for computing multiplication over a class of GF(2m) based on both irreducible all one polynomials (AOPs) and equally spaced polynomials (ESPs). The proposed AOP-based multiplier uses the modified Booth's algorithm to develop a new multiplexer-based bit-parallel multiplier that is simple and modular and such properties are important for VLSI hardware implementation. The multiplier requires ⌈m/4⌉(m + 1) MUX4 x 1 and (1.5m2 + 0.5m - 1) XOR gates. Its time delay is not greater than TM + (3 + log2⌈m/4⌉)TX, where TM and TX are the time delays of MUX4 x 1 and 2-input XOR gate, respectively. For a certain degree, an irreducible ESP with a high degree can be obtained from a corresponding irreducible AOP with a relatively very low degree. Using the subword parallel processing, the proposed AOP-based multiplier with low degree can also be adopted to realize ESP-based multipliers with high degrees.