Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Automated BIST for Sequential Logic Synthesis
IEEE Design & Test
Testability analysis and insertion for RTL circuits based on pseudorandom BIST
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Synthesizing for Scan Dependence in Built-In Self-Testable Designs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Making the Circular Self-Test Path Technique Effective for Real Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
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This paper analyzes the random pattern testability of faults in the control logic of an embedded memory. We show how to compute exposure probabilities of these faults using mostly signal probability computations. We also show that the hardest memory control logic fault to detect is not necessarily the one with the lowest detection probability at the memory boundary.