Test generation systems in Japan
DAC '75 Proceedings of the 12th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Defect Level as a Function of Fault Coverage
IEEE Transactions on Computers
Using scan technology for debug and diagnostics in a workstation environment
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Why Can't DFT Totally Eliminate Functional Test?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
On-Chip Delay Measurement Based Response Analysis for Timing Characterization
Journal of Electronic Testing: Theory and Applications
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Techniques are described that target extending usability ofexiting scan-based DFT approaches for activities beyond ICcomponent testing. In particular, the need for applyingDFT to improve product Time-to-Market is described andjustified. This need is evident from observations that aSystem on a Chip (SoC) design poses serious designverification challenges that may impact overall productsuccess in ways that can not be compensated for byimproving product quality. DFT features are described thatthat bring system-level diagnostics tools, such as the systemLogic Analyzer and the Service Processor, to the IC level inorder to facilitate post-silicon debug and verification.Finally, it is pointed out that much work remains to be doneby existing EDA companies (or new entrepreneurialcompanies) to provide new tools that integrate the newDFT features into the SoC synthesis flow.