Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
IEEE Transactions on Computers
Design for Testability: It is time to deliver it for Time-to-Market
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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An architecture for implementing scan technology for test and debug in a state-of-the-art workstation is described. Architectural features include controlling the scan and clock functions from a single resource which can also perform Linear Feedback Shift Register (LFSR) based pseudo-random testing and test-result compression via signature capture. Operations of the scan subsystem are controlled from a Service Processor which uses a Diagnostics Bus to communicate with individual Scan and Clock Resource units present on each system board. For debug purposes the Service Processor has been linked with a remote computer and software has been developed to display and/or modify system state variables (flip-flops), Analysis of scan overhead indicate that benefits in test and debug of the target system far outweigh the cost of implementing scan technology for the APOLLO DN 10000 workstation.