Test generation systems in Japan
DAC '75 Proceedings of the 12th Design Automation Conference
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This paper describes a new heuristic algorithm for the computation of tests to detect failures in sequential logic circuits. In the algorithm, the values of logic blocks in a logic circuit are expressed in boolean vectors with six elements and main process of the algorithm is the operations among these values. Presented in this paper are basic principles for the algorithm, their application procedure with an example and our experiences through the implemented system.