Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
Synapse: An Expert System for VLSI Design
Computer - Special issue on expert systems in engineering
Design for testability — a review of advanced methods
Microprocessors & Microsystems
Design of Testable VLSI Circuits with Minimum Area Overhead
IEEE Transactions on Computers
A knowledge based system for selecting a test methodology for a PLA
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
WEAVER: a knowledge-based routing expert
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Threading of multiple scan paths in a VLSI circuit
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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To tackle the current day testing complexity of VLSI circuits Design For Testability (DFT) is becoming more of a necessity. However VLSI designers are yet to accept DFT mainly due to lack of effective tools. Expert Systems technology promises to be an useful means to present to the designer the gamut of DFT knowledge developed so far, primarily by test experts, in a more effective way. DFTEXPERT is an attempt towards this direction. This paper presents the major components of DFTEXPERT and also demonstrates its capability through a small illustration.