Artificial intelligence
Test Schedules for VLSI Circuits Having Built-In Test Hardware
IEEE Transactions on Computers - The MIT Press scientific computation series
PHRAN-SPAN: a natural language interface for system specifications
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
DFTEXPERT: an expert system for design of testable VLSI circuits
IEA/AIE '88 Proceedings of the 1st international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 1
VLSI design synthesis with testability
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The ADAM advanced design automation system: overview, planner and natural language interface
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
PLAXPERT—an expert system for incorporating design for testability in programmable logic arrays
CSC '88 Proceedings of the 1988 ACM sixteenth annual conference on Computer science
A Knowledge-Based System for Selecting Test Methodologies
IEEE Design & Test
DFT Expert: Designing Testable VLSI Circuits
IEEE Design & Test
A knowledge representation scheme for DFT
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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Testability is a very important aspect of VLSI circuits. Numerous design for testability (DFT) methods exist. Often designers face the complex problem of selecting the best DFT techniques for a particular chip under a set of design constraints and goals. In order to aid in designing testable circuits, a prototype knowledge based system has been developed which simulates a human expert on design of testable PLAs. The system, described in this paper, has knowledge about testable PLA design methodologies and is able to negotiate with the user so as to lead the user through the design space to find a satisfactory solution. A new search strategy, called reason analysis, is introduced.