Test generation for Gigahertz processors using an automatic functional constraint extractor
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Orthogonal Scan: Low-Overhead Scan for Data Paths
Proceedings of the IEEE International Test Conference on Test and Design Validity
Pentium® Pro Processor Design for Test and Debug
Proceedings of the IEEE International Test Conference
Testability Features of the SuperSPARCtm
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
CHEETA: Composition of Hierarchical Sequential Tests Using ATKET
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Fast hierarchical test path construction for DFT-free controller-datapath circuits
ATS '00 Proceedings of the 9th Asian Test Symposium
A Knowledge-Based System for Designing Testable VLSI Chips
IEEE Design & Test
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Data Path Direct Access Test, DPDAT, supportsefficient structural test of targeted datapath blocksusing existing non-datapath DFT features inconjunction with architectural transparency alreadypresent in surrounding datapath blocks. This newDFT technique allows ATPG patterns generated atlogic block levels to be applied at the full chipwithout expensive DFT overhead. The results ofinvestigating feasibility on Intel® Pentium® 4 showexistence of these natural transparent paths, lowarea overhead and high fault coverage usingsequential ATPG techniques under DPDAT.