A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
A Knowledge-Based System for Designing Testable VLSI Chips
IEEE Design & Test
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Test challenges posed by VLSI devices in the areas of AC testing and throughput have led to the development of a rules based Automatic Test Program Generator (ATPG) that integrates IBM's CAD system with a "per-pin" tester. This paper describes the versatility of the ATPG that gleans test patterns and the logic model from the CAD system, merges product technology characteristics and generates a complete test program that verifies the electrical, functional and timing integrity of the device under test.