Introductory Guide to Silvar Lisco and Hilo Simulators
Introductory Guide to Silvar Lisco and Hilo Simulators
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Rule Based Expert Systems: The Mycin Experiments of the Stanford Heuristic Programming Project (The Addison-Wesley series in artificial intelligence)
A Knowledge-Based System for Designing Testable VLSI Chips
IEEE Design & Test
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CAD-generated component and interconnection listings are utilised to recreate a circuit design in the form of an associative network. This is stored within an expert system's database and enables a powerful search algorithm, under the guidance of testability formulation rules, to explore the circuit. The algorithm interacts with these device models and register transfer logic based device operation rules to identify valid test paths through a circuit and thus define functional tests. Once identified, the tests are ordered (using rule-based and heuristic techniques) in terms of increasing test complexity to aid diagnostics. Finally, the test paths are passed on to a low-level test timing generator to produce the actual test vectors required to test the board.