GSP: A logic simulator for LSI
DAC '81 Proceedings of the 18th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
A heuristic chip-level test generation algorithm
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
IEEE Design & Test
Test Synthesis with Alternative Graphs
IEEE Design & Test
Efficient Hierarchical Approach to Test Generation for Digital Systems
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
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Functional fault modeling and simulation for VLSI devices is described(*). A functional fault list is compiled using model perturbation and mapping of circuit defects into functional faults. A set of test vectors is then derived which detects all faults in the functional fault list. This same test vector set is then applied to a gate level model of the device. For the test case analyzed, a very high level of equivalent gate coverage was achieved. Conclusions are drawn as to the effectiveness of the technique and how amenable it is to automation.