Fast sequential circuit test generation using high-level and gate-level techniques
Proceedings of the conference on Design, automation and test in Europe
Quality Testing Requires Quality Thinking
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Hierarchical Defect-Oriented Fault Simulation for Digital Circuits
ETW '00 Proceedings of the IEEE European Test Workshop
Inductive Fault Analysis of MOS Integrated Circuits
IEEE Design & Test
Testing strategies for networks on chip
Networks on chip
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A generalized approach is presented to fault simulation and test generation based on a uniform functional fault model for different system representation levels. The fault model allows to represent the defects in components and defects in the communication network of components by the same technique. Physical defects are modeled as parameters in generalized differential equations. Solutions of these equations give the conditions at which defects are locally activated. The defect activation conditions are used as functional fault models for the higher level fault simulation purposes. In such a way, the functional fault model can be regarded as interface for mapping faults from one system level to another, helping to carry out hierarchical fault simulation and test generation in digital systems. A methodology is proposed which allows to find the types of faults that may occur in a real circuit, to determine their probabilities, and to find the input test patterns that detect these faults. Experimental data of the hierarchical defect-oriented simulation for ISCAS'85 benchmarks are presented, which show that classical stuck-at fault based simulation and the test coverage calculation based on counting defects without considering defect probabilities may lead to considerable overestimation of results.