Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Sequential circuit test generation in a genetic algorithm framework
DAC '94 Proceedings of the 31st annual Design Automation Conference
Arithmetic built-in self-test for embedded systems
Arithmetic built-in self-test for embedded systems
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Structured Logic Testing
Testing the Interconnect of RAM-Based FPGAs
IEEE Design & Test
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Accumulator based deterministic BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Defect-Oriented Fault Simulation and Test Generation in Digital Circuits
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
A novel pattern generator for near-perfect fault-coverage
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Toward a scalable test methodology for 2D-mesh Network-on-Chips
Proceedings of the conference on Design, automation and test in Europe
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The complexity of Networks-on-Chip (NoC) makes the application of traditional test methods obsolete. For NoC, a combination of methods known from the System-on-Chip, memory and FPGA test areas should be used. That includes functional test, scan test, logic BIST, RAM BIST and testing of interconnect switches and wires. The increasing complexities of systems based on deep-submicron technologies cause two contrary trends: low-level defect-orientation to reach the high reliability of testing and high-level behavioral modeling to reach the efficiency of test generation. Hierarchical approaches seem to be the solution. Built-In Self-Test (BIST) is the main concept for testing the cores in systems on chip. Hybrid BIST containing both hardware and software components is probably the most promising approach to test the nodes of NoC. In densely packaged NoC with embedded memories and reusable cores scan-based approaches, P1500 standard for core test, test access mechanisms, test controt and isolation issues are prospective methods. Testing the NoC interconnect switches and wires is also an important issue.