Characterization of Floating Gate Defects in Analog Cells
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Analog and Mixed-Signal Benchmark Circuits-First Release
Proceedings of the IEEE International Test Conference
Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Optimal Conditions for Boolean and Current Detection of Floating Gate Faults
ITC '99 Proceedings of the 1999 IEEE International Test Conference
BIST for Phase-Locked Loops in Digital Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Inductive Fault Analysis of MOS Integrated Circuits
IEEE Design & Test
Testing Biquad Filters under Parametric Shifts Using X-Y Zoning
Journal of Electronic Testing: Theory and Applications
Multi-VDD Testing for Analog Circuits
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Adaptive Fault Diagnosis of Analog Circuits by Operation-Region Model and X---Y Zoning Method
Journal of Electronic Testing: Theory and Applications
Verifying functional specifications by regression techniques on Lissajous test signatures
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A Level-Crossing Approach for the Analysis of RF Modulated Signals Using Only Digital Test Resources
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
A new Built-In Self-Test structure, based onthe information provided by the XY-operation(Lissajous curves) is introduced in this paper. ADigital Signature is obtained which is used todiscriminate catastrophic as well as parametricdefects. High Fault Coverage is achieved whenapplying the proposed BIST on an ITC'97 benchmarkcircuit where 92% of the catastrophic defects and87.5% of the parametric defects analyzed produceddigital signatures clearly distinguishable from thegolden signature.