On-chip Analog Response Extraction with 1-Bit Ε Δ- Modulators
ATS '02 Proceedings of the 11th Asian Test Symposium
7.2 Enhancing Test Effectiveness for Analog Circuits Using Synthesized Measurements
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Digital Signature Proposal for Mixed-Signal Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Frequency-based BIST for analog circuit testing
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Low Cost Analog Testing of RF Signal Paths
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Dynamic Analog Testing via ATE Digital Test Channels
ATS '04 Proceedings of the 13th Asian Test Symposium
Low-Cost Alternate EVM Test for Wireless Receiver Systems
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Exploiting Zero-Crossing for the Analysis of FM Modulated Analog/RF Signals Using Digital ATE
ATS '09 Proceedings of the 2009 Asian Test Symposium
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The test of analog & RF circuits at wafer-level suffers from both quality and throughput limitations, especially due to probing issues and limited count of expensive instrumentation resources. Since final test after packaging guarantees product performances, constraints on wafer-level test can be relaxed. This paper investigates a signal acquisition protocol based on the use of digital tester channels to perform the demodulation of analog/RF signals. Due to the large availability of such hardware resources on most testers, this approach allows to setup a multi-site strategy, thus increasing the test throughput. The fundamental concept is to capture the signal through the 1-bit comparator available in a digital tester channel and to process the resulting bit stream to retrieve the analog/RF signal characteristics. In this paper, the proposed solution is illustrated for the demodulation of Frequency-Modulated (FM) and Amplitude-Modulated (AM) signals. Both simulation and experimental results obtained with a Verigy 93K platform are presented.