An algorithm for diagnosing two-line bridging faults in combinational circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Algorithms for IDDQ measurement based diagnosis of bridging faults
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
Diagnosis of realistic bridging faults with single stuck-at information
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Defect Classes - An Overdue Paradigm for CMOS IC
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Beyond the Byzantine Generals: Unexpected Behaviour and Bridging Fault Diagnosis
Proceedings of the IEEE International Test Conference on Test and Design Validity
Inductive Fault Analysis of MOS Integrated Circuits
IEEE Design & Test
Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability
IEEE Transactions on Computers
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Effective bridging fault diagnosis requires reducing the (n/2) number of bridging faults to a handful of candidates. A preliminary step can reduce the 0(n2) candidates to a manageable 0(n) candidates by using layout information to eliminate those bridging faults that are very likely to be shorted together. This step removes from consideration those faults that match the fault signature but are physically impossible. However, sometimes 驴 perhaps due to issues of intellectual property or because the degree of information stored about a circuit changes over its lifecycle 驴 the physical design of the circuit is not available, and the number of nodes is too large to explicitly consider all pairs. In this paper we presenttwo ways to provide successful diagnosis without access to physical information. The second method produces optimal diagnosis under our ranking criteria. Either technique can be used in conjunction with information extracted from the physical design to allow for diagnosis of much larger circuits than previously possible.