On achieving a complete fault coverage for sequential machines using the transition fault model
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Observations on the Effects of Fault Manifestation as a Function of Workload
IEEE Transactions on Computers - Special issue on fault-tolerant computing
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Zamlog: a parallel algorithm for fault simulation based on Zambezi
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Test Sets and Reject Rates: All Fault Coverages are Not Created Equal
IEEE Design & Test
Synthesis for testability of large complexity controllers
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Inductive Fault Analysis of MOS Integrated Circuits
IEEE Design & Test
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
DAC '98 Proceedings of the 35th annual Design Automation Conference
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Test generation algorithms may be classified by the level of circuit description they utilize. Algorithms based on a logic-gate level description of the circuit under test (CUT) are the most common. Functional algorithms utilize a functional description of the CUT. Functional test generation techniques may provide better defect coverages than do purely logic-level techniques. Multilevel test generation algorithms attempt to realize the advantages of both approaches by utilizing fault translation. Here, gate-level faults are translated to functional faults and test generation is performed at the functional level. In this paper, we develop and present new techniques for fast efficient fault translation from the logic to the functional level. These techniques are implemented in a multilevel sequential circuit test generation system. The performance of the system is investigated on benchmark circuits.