Fault simulation on massively parallel SIMD machines: algorithms, implementations and results
Journal of Electronic Testing: Theory and Applications
Parallel logic and fault simulation algorithms for shared memory vector machines
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A parallel algorithm for fault simulation based on PROOFS
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Data parallel fault simulation
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Asynchronous parallel algorithms for test set partitioned fault simulation
Proceedings of the eleventh workshop on Parallel and distributed simulation
SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a new multiprocessor sequential circuit fault simulator, Zamlog, based on a novel uniprocessor simulator, Zambezi. Both the fault and test sets are partitioned for multiprocessor simulation. The parallelization technique, designed to preserve the efficiency of Zambezi, is simple to implement and has low communication requirements. Experimental results indicate that Zamlog can obtain speedups of up to 95. The speedups obtained and the scalability are between 3 and 10 times better than any reported in the literature. Furthermore, the speed-ups obtained are with respect to a uniprocessor algorithm which is superior, by an average of 40%, to those used to gauge the speed-ups of previous parallel systems.