ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator

Authors:
M. B. Amin;B. Vinnakota
Affiliations:
-;-
Venue:
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Year:
1996

Citing 0
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Abstract

Sequential circuit fault simulators use the multiple bits in a computer data word to accelerate simulation. We introduce, and implement, a new sequential circuit fault simulator, a parallel pattern parallel fault simulator, ZAMBEZI, which simultaneously simulates multiple faults with multiple vectors in one data word. ZAMBEZI is developed by enhancing the control flow, of existing parallel pattern algorithms. For a very wide range of benchmark circuits, compared to parallel fault and parallel pattern simulators, ZAMBEZI offers either the best, or very close to the best, uniprocessor performance. ZAMBEZI also offers superior performance when parallelized.