Parallel test generation for sequential circuits on general-purpose multiprocessors
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Concurrent fault simulation of logic gates and memory blocks on message passing multicomputers
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Parallel algorithms for VLSI computer-aided design
Parallel algorithms for VLSI computer-aided design
Using MPI: portable parallel programming with the message-passing interface
Using MPI: portable parallel programming with the message-passing interface
Zamlog: a parallel algorithm for fault simulation based on Zambezi
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A parallel algorithm for fault simulation based on PROOFS
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Automatic test generation using genetically-engineered distinguishing sequences
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Asynchronous parallel algorithms for test set partitioned fault simulation
Proceedings of the eleventh workshop on Parallel and distributed simulation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Efficient fault simulation on many-core processors
Proceedings of the 47th Design Automation Conference
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We propose three synchronous parallel algorithms for scalable parallel test set partitioned fault simulation. The algorithms are based on a new two-stage approach to parallelizing fault simulation for sequential VLSI circuits in which the test set is partitioned among the available processors, The test set partitioning inherent in the algorithms overcomes the good circuit logic simulation bottleneck that exists in traditional fault partitioned approaches to parallel fault simulation. The implementations were done on a shared memory multiprocessor and on a network of workstations. Two of the algorithms show a small degree of pessimism in a few cases, with respect to the fault coverage as compared with a uniprocessor run, while the third algorithm provides the same results as in a uniprocessor run. All algorithms provide excellent speedups and perform much better than a traditional fault partitioned approach, on both shared and distributed memory parallel platforms.