Design and Implementation of a Parallel Automatic Test Pattern Generation Algorithm with Low Test Vector Count

Authors:
Robert Butler;Brion Keller;Sarala Paliwal;Richard Schoonover
Affiliations:
-;-;-;-
Venue:
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Year:
2000

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Abstract

We present an implementation for parallel ATPGthat is constructed so as to achieve a test vector countcomparable to the serial algorithm. This task posed achallenge since unlike previous published works,substantial effort is applied in the serial algorithm to keepthe test vector count low. Results on industrial circuitsthat range in size from 700,000 gates to about 3 million gates are presented. Previous works have publishedresults for smaller circuits.