Differential fault simulation - a fast method using minimal memory
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Parallel test generation for sequential circuits on general-purpose multiprocessors
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Concurrent fault simulation of logic gates and memory blocks on message passing multicomputers
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Parallel algorithms for VLSI computer-aided design
Parallel algorithms for VLSI computer-aided design
New methods of improving parallel fault simulation in synchronous sequential circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A parallel algorithm for fault simulation based on PROOFS
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
The concurrent simulation of nearly identical digital networks
DAC '73 Proceedings of the 10th Design Automation Workshop
ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
A Deductive Method for Simulating Faults in Logic Circuits
IEEE Transactions on Computers
Asynchronous parallel algorithms for test set partitioned fault simulation
Proceedings of the eleventh workshop on Parallel and distributed simulation
SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Parallelizing post-placement timing optimization
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
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We propose a new approach to parallelizing fault simulation in which the test set is partitioned among the available processors. The approach can be used for any of the sequential circuit fault simulation algorithms commonly used, and it can be implemented on various different parallel architectures. This approach for the first time overcomes the limitations of serial logic simulation. In addition, the excessive redundant computations required in the traditional fault-partitioning approach are also considerably reduced. Significant improvements in speedup were observed as compared to previous approaches. An average speedup of 5.7 was obtained for test set partitioning over 10 processors for the benchmark circuits studied. Although pessimistic fault coverage may be reported in some cases, the proposed approach was found to be very accurate for the circuits studied.