Fault simulation on massively parallel SIMD machines: algorithms, implementations and results
Journal of Electronic Testing: Theory and Applications
Parallel algorithms for VLSI computer-aided design
Parallel algorithms for VLSI computer-aided design
Data parallel fault simulation
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Towards acceleration of fault simulation using graphics processing units
Proceedings of the 45th annual Design Automation Conference
Fault Table Computation on GPUs
Journal of Electronic Testing: Theory and Applications
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Simulation at the gate level is computationally very expensive.Parallel processing is one technique to reduce simulation time.Possessing knowledge of the distribution of computational activity insimulation can aid in parallelizing it efficiently. We present a newcharacterization of the distribution of the computational workload infault simulation. An empirical analysis shows that the workloaddistribution is circuit specific, and is largely independent of thevector set being simulated. An inexpensive method to predict theworkload distribution is also discussed.