A protocol test generation procedure
Computer Networks and ISDN Systems
On achieving a complete fault coverage for sequential machines using the transition fault model
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
FsmTest: functional test generation for sequential circuits
Integration, the VLSI Journal
Testing Finite-State Machines: State Identification and Verification
IEEE Transactions on Computers
Protocol Conformance Testing Using Multiple UIO Sequences
Proceedings of the IFIP WG6.1 Ninth International Symposium on Protocol Specification, Testing and Verification IX
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Generating optimal distinguishing sequences with a model checker
A-MOST '05 Proceedings of the 1st international workshop on Advances in model-based testing
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Unique input/output(UIO) sequences are used for state verification and functional test in finite state machines. A UIO sequence for a state s distinguishes it from other states in the FSM. Current algorithms to compute UIO sequences are limited in their applicability to FSMs with binary input symbols such as those found in con trol applications. Execution times of traditional approaches are exponential in the n umber of FSM inputs. We dev elop a new heuristic algorithm to generate UIO sequences for FSMs with binary inputs. Execution time is reduced significantly b y reducing the size of the search space. When a UIO sequence cannot be generated, our algorithm generates a small n umber of functional faults for state verification.