A Survey of Multivalued Memories
IEEE Transactions on Computers
Switch-level testability of the dynamic CMOS PLA
Integration, the VLSI Journal
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Tutorial on semiconductor memory testing
Journal of Electronic Testing: Theory and Applications - Special issue: on memory testing
Development of Fault Model and Test Algorithms for Embedded DRAMs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Automatic Failure-Analysis System for High-Density DRAM
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Inductive Fault Analysis of MOS Integrated Circuits
IEEE Design & Test
Fault Models and Tests for a 2-Bit-per-Cell MLDRAM
IEEE Design & Test
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This paper describes the development of a fault model and testing strategies for a 2-bit per cell dynamic random-access memory (DRAM). Multilevel DRAM technology may become an important way of increasing the storage density of semiconductor memory for a given process and minimum feature size. The Gillingham multilevel DRAM that we consider employs a multi-step sensing and restoring technique that re-uses many proven elements from a conventional 1-bit per cell DRAM cell array. Starting with a list of reported DRAM physical defects, we develop a logical fault model using both manual circuit analysis and analog circuit simulation. Several alternative testing strategies are proposed that make different trade-offs between testing cost and possible design for testability enhancements.