A Survey of Multivalued Memories
IEEE Transactions on Computers
Switch-level testability of the dynamic CMOS PLA
Integration, the VLSI Journal
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Development of Fault Model and Test Algorithms for Embedded DRAMs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Fault Models and Test Strategies for a Two-Bit per Cell DRAM
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
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This article presents a fault model and testing strategies for a 2-bit per cell dynamic random-access memory (DRAM). Multilevel DRAM technology may become an important way of increasing the storage density of semiconductor memory for a given process and minimum feature size. The multilevel DRAM that we consider re-uses many proven elements from a conventional 1-bit per cell DRAM cell array. From a list of reported DRAM physical defects we develop a fault model using both manual analysis and analog simulation. Several alternative testing strategies are proposed that make different trade-offs between testing cost and possible design for testability enhancements.