BiCMOS logic testing

Authors:
Marc E. Levitt;Kaushik Roy;Jacob A. Abraham
Affiliations:
Sun Microsystems, Mountain View, CA;Department of Electrical Engineering, Purdue University, West Lafayette, IN;Computer Engineering Research Center, University of Texas at Austin, Austin, TX
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
1994

Citing 6
Cited 0

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Synthesis and optimization procedures for robustly delay-fault testable combinational logic circuits

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Testability analysis and fault modeling of BiCMOS circuits

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Analysis of Steady State Detection of Resistive Bridging Faults in BiCMOS Digital ICs

Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Inductive Fault Analysis of MOS Integrated Circuits

IEEE Design & Test

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Abstract

With the anticipated growth of BiCMOS technology for high-performance ASIC design, the issue of testing takes on great significance. This paper addresses the testing of BiCMOS logic circuits. Since many different implementations of BiCMOS gates have been proposed, four representative ones are studied. The adequacy of stuck-at, quiescent current, and delay testing are examined based on circuit level faults. It is demonstrated that a large portion of the defects cannot be detected by common stuck-at or quiescent current tests since they manifest themselves as delay faults. By using the results presented, the test methodologies and the logic families can be ranked based on fault coverage. This ranking can then be used to help decide which BiCMOS solution is proper for a given application.