Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Using March Tests to Test SRAMs
IEEE Design & Test
Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique
Proceedings of the IEEE International Test Conference on Test and Design Validity
Memory built-in self-repair using redundant words
Proceedings of the IEEE International Test Conference 2001
An experimental analysis of spot defects in SRAMs: realistic fault models and tests
ATS '00 Proceedings of the 9th Asian Test Symposium
6.1 IDDQ Testing of Opens in CMOS SRAMs
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
Reducing Test Time of Embedded SRAMs
MTDT '03 Proceedings of the 2003 International Workshop on Memory Technology, Design and Testing
Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Inductive Fault Analysis of MOS Integrated Circuits
IEEE Design & Test
A parallel transparent BIST method for embedded memory arrays by tolerating redundant operations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
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Increasingly dense SRAMs of various bit capacities,embedded within current and future Systems-on-a-Chip(SoC) designs, command not only additional complexitydue to required redundancy schemes, but also presentserious challenges in regards to testing. In particular, thetime needed for testing data retention faults (DRFs) andNon-DRFs is growing rapidly. In this paper, we considerthe Overall Production Gain (OPG) and delay timeassociated with the testing of DRFs as the two selectionfactors for classifying embedded SRAMs, where OPGquantifies the trade-offs between yield and redundancyarea overhead. These embedded SRAMs are categorizedinto four categories for testing Non-DRFs and DRFs.Since both factors above are related to memory capacity,the four categories are named as very small, small, large,and very large types. According to this simpleclassification, we generate a set of four March testalgorithms from an existing March SRD algorithm foreach category respectively. As a comparison with MarchSRD, our investigations reveal that test time can generallybe at least halved down to 22nm technology for allcapacity e-SRAMs with different IO numbers withoutlosing defect coverage. The evaluation results also showthat this reduction ratio is always no less than 50% forthose with larger and larger and larger capacitypredicted for future e-SRAMs in ITRS documents nomatter what complex the comparison algorithms besidesMarch SRD are.