Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Reducing the CMOS RAM test complexity with IDDQ and voltage testing
Journal of Electronic Testing: Theory and Applications
Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique
Proceedings of the IEEE International Test Conference on Test and Design Validity
Reducing Embedded SRAM Test Time under Redundancy Constraints
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A retention-aware test power model for embedded SRAM
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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The behavior of a CMOS SRAM memory in the presence of open defects is analyzed. It has been found that destructive read-out depends on the level of the precharge. Two techniques to test open defects producing data retention faults are proposed. In the first technique an initial condition is forced during the writing phase. In this way, intermediate voltages appear during the memorizing phase. Hence, the quiescent current consumption (IDDQ) increases and the fault can be detected sensing the IDDQ. A second technique controlling the power supply level in conjunction with sequential access is proposed. This allows detection of open defects by IDDQ testing. The cost of both proposed approachs is analyzed.