Physical DFT for High Coverage of Realistic Faults

Analysis of switch-level faults by symbolic simulation

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

VHDL fault simulation for defect-oriented test and diagnosis of digital ICs

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation

Defect-Oriented Sampling of Non-Equally Probable Faults in VLSI Systems

Journal of Electronic Testing: Theory and Applications

Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits

EDTC '95 Proceedings of the 1995 European conference on Design and Test

13.2 Sampling Techniques of Non-Equally Probable Faults in VLSI Systems

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Incorporating Physical Design-For-Test Into Routing

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Back annotation of physical defects into gate-level, realistic faults in digital ICs

ITC'94 Proceedings of the 1994 international conference on Test

Simulation results of an efficient defect analysis procedure

ITC'94 Proceedings of the 1994 international conference on Test